november 1998 f dg 6 320 c dual n & p c hannel digital fet general description features absolute maximum ratings t a = 25 o c unless other wise noted symbol parameter n-channel p-channel units v ds s drain-source voltage 25 -25 v v gss gate-source voltage 8 -8 v i d drain current - continuous 0.22 -0.14 a - pulsed 0.65 -0.4 p d maximum power dissipation (note 1) 0.3 w t j ,t stg operating and storage temper ature range r -55 to 150 c esd electrostatic discharge rating mil-std-883d human body model (100pf / 1500 ohm) 6 kv thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1 ) 415 c/w fdg 6320 c rev. d n-ch 0.22 a , 25 v , r ds(on) = 4.0 w @ v gs = 4.5 v, r ds(on) = 5.0 w @ v gs = 2.7 v. p -ch -0.14 a , -25v , r ds(on) = 10 w @ v gs = -4.5v, r ds(on) = 13 w @ v gs = -2.7 v. very small package outline sc70-6. very l ow level gate drive requirements allowing direct operation in 3 v circuits (v gs(th) < 1.5 v). gate-source zener for esd ruggedness (>6 kv human body model). these dual n & p-c hannel logic level enhancement mode field effect transistors are produced using fairchild 's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance. this device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal mosfets . since bias resistors are not required, this dual digital fet can replace several different digital transistors, w ith different bias resistor values. sc70-6 supersot t m -6 soic-14 so-8 sot-8 sot-23 d1 s2 g1 d2 s1 g2 sc70-6 .20 pin 1 5 3 2 4 1 6 ? 1998 fairchild semiconductor corporation
electrical characteristics ( t a = 25 o c unless otherwise noted ) symbol parameter conditions type min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a n-ch 25 v v gs = 0 v, i d = -250 a p-ch -25 d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c n-ch 25 mv/ o c i d = -250 a , referenced to 25 o c p-ch -19 i dss zero gate voltage drain current v ds = 20 v, v gs = 0 v, n-ch 1 a t j = 5 5c 10 i dss zero gate voltage drain current v ds =-20 v, v gs = 0 v , p-ch -1 a t j = 5 5c -10 i gss gate - body leakage current v gs = 8 v, v ds = 0 v n-ch 100 na v gs = - 8 v, v ds = 0 v p-ch -100 na on characteristics (note 2) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a n-ch 0.65 0.85 1.5 v v ds = v gs , i d = -250 a p-ch -0.65 -0.82 -1.5 d v gs(th) / d t j gate threshold voltage temp. coefficient i d = 250 a , referenced to 25 o c n-ch -2.1 mv/ o c i d = -250 a , referenced to 25 o c p-ch 2.1 r ds(on) static drain-source on-resistance v gs = 4.5 v, i d = 0.22 a n-ch 2.6 4 w t j =12 5c 5.3 7 v gs = 2.7 v, i d = 0.19 a 3.7 5 v gs = -4.5 v, i d = -0.14 a p-ch 7.3 10 t j =12 5c 11 17 v gs = -2.7 v, i d = -0.05 a 10.4 13 i d(on) on-state drain current v gs = 4.5 v, v ds = 5 v n-ch 0.22 a v gs = -4.5 v, v ds = -5 v p-ch -0.14 g fs forward transconductance v ds = 5 v, i d = 0.22 a n-ch 0.2 s v ds = -5 v, i d = -0.14 a p-ch 0.12 dynamic characteristics c iss input capacitance n-channel n-ch 9.5 pf v ds = 10 v, v gs = 0 v, p-ch 12 c oss output capacitance f = 1.0 mhz n-ch 6 p-channel p-ch 7 c rss reverse transfer capacitance v ds = -10 v, v gs = 0 v, n-ch 1.3 f = 1.0 mhz p-ch 1.5 fdg 6320 c rev. d
electrical characteristics ( continued ) switching ch aracteristics (note 2 ) symbol parameter conditions type min typ max units t d(on ) turn - on delay time n-channel n-ch 5 12 ns v dd = 5 v, i d = 0.5 a , p-ch 5 12 t r turn - on rise time v gs = 4.5 v, r gen = 50 w n-ch 4.5 10 ns p-ch 8 16 t d(off) turn - off delay time p-channel n-ch 4 8 ns v dd = -5 v, i d = -0.5 a, p-ch 9 18 t f turn - off fall time v gs = -4.5 v, r gen = 50 w n-ch 3.2 7 ns p-ch 5 12 q g total gate charge n-channel n-ch 0.29 0.4 nc v ds = 5 v, i d = 0.22 a, p-ch 0.22 0.31 q gs gate-source charge v gs = 4.5 v n-ch 0.12 nc p- channel p-ch 0.12 q gd gate-drain charge v ds = -5 v, i d = -0.14 a, n-ch 0.03 nc v gs = -4.5 v p-ch 0.05 drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current n-ch 0.25 a p-ch -0.25 v sd drain-source diode forward voltage v gs = 0 v, i s = 0 .5 a (note 2 ) n-ch 0.8 1.2 v v gs = 0 v, i s = -0 .5 a (note 2 ) p-ch -0.8 -1.2 notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. r q ja = 415 o c/w on minimum mounting pad on fr-4 board in still air. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. fdg 6320 c rev. d
fdg 6320 c .rev d typical electrical characteristics: n-channel figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . figure 3. on-resistance variation with temperature . figure 5 . transfer characteristics. figure 4 . on-resistance variation with gate-t o -source voltage. -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 1.8 t , junction temperature (c) drain-source on-resistance j r , normalized ds(on) v = 4.5v gs i = 0.22a d 0 1 2 3 4 5 0 0.1 0.2 0.3 0.4 0.5 v , drain-source voltage (v) i , drain-source current (a) v =4.5v gs ds d 2.5v 3.0v 2.0v 3.5v 2.7v 0 0.1 0.2 0.3 0.4 2 2.5 3 3.5 4 4.5 5 i , drain current (a) drain-source on-resistance v = 2.5v gs d r , normalized ds(on) 5.0v 4.5v 2.7v 4.0v 3.5v 3.0v 1 2 3 4 5 0 4 8 12 16 20 v ,gate to source voltage (v) r , on-resistance(ohm) gs ds(on) 25c i = 0.10a d t =125c a 0.5 1 1.5 2 2.5 3 0 0.05 0.1 0.15 0.2 v , gate to source voltage (v) i , drain current (a) v = 5v ds gs d t = -55c j 125c 25c 0 0.2 0.4 0.6 0.8 1 1.2 0.0001 0.001 0.01 0.1 0.4 v , body diode forward voltage (v) i , reverse drain current (a) 25c -55c v = 0v gs sd s t = 125c j figure 6 . body diode forward voltage varia tion with source current and temperature.
fdg 6320 c .rev d typical electrical characteristics: n-channel (continued) figure 10 . single pulse maximum power dissipation. figure 8. capacitance characteristics . figure 7 . gate charge characteristics. 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 q , gate charge (nc) v , gate-source voltage (v) g gs i = 0.22a d v = 5v ds 10v figure 9. maximum safe operating area. 0.4 0.8 2 5 10 25 40 0.01 0.03 0.1 0.3 1 v , drain-source voltage (v) i , drain current (a) rds(on) limit d dc ds 10s 100ms 10ms v = 4.5v single pulse r = 415 c/w t = 25c q ja gs a 1s 0.1 0.3 1 3 10 25 2 3 5 8 15 30 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0 v gs c oss c rss 0.0001 0.001 0.01 0.1 1 10 200 0 10 20 30 40 50 single pulse time (sec) power (w) single pulse r =415c/w t = 25c q ja a
fdg 6320 c .rev d typical electrical characteristics: p-channel figure 11. on-region characteristics . figure 12. on-resistance variation with drain current and gate voltage . figure 13. on-resistance variation with temperature . figure 15 . transfer characteristics. figure 14 . on-resistance variation with gate-t o -source voltage. figure 16 . body diode forward voltage varia tion with source current and temperature. -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j r , normalized ds(on) v = -4.5v gs i = -0.14a d 0 1 2 3 4 0 0.05 0.1 0.15 0.2 -v , drain-source voltage (v) -i , drain-source current (a) v = -4.5v gs ds d -2.7v -3.0v -3.5v -2.0v -2.5v 0 0.05 0.1 0.15 0.2 0.5 1 1.5 2 2.5 -i , drain current (a) drain-source on-resistance v = -2.0v gs d r , normalized ds(on) -4.5v -4.0v -3.0v -2.7v -3.5v -2.5v 1.5 2 2.5 3 3.5 4 4.5 5 0 5 10 15 20 25 -v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) i = -0.07a d t = 125c a t = 25c a 0 1 2 3 4 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 -v , gate to source voltage (v) -i , drain current (a) v = -5.0v ds gs d t = -55c a 125c 25c 0.2 0.4 0.6 0.8 1 1.2 0.0001 0.001 0.01 0.1 0.3 -v , body diode forward voltage (v) -i , reverse drain current (a) t = 125c a 25c -55c v = 0v gs sd s
fdg 6320 c .rev d typical electrical characteristics: p-channel (continued) figure 2 0 . single pulse maximum power dissipation. figure 18 . capacitance characteristics . figure 17 . gate charge characteristics. figure 19. maximum safe operating area. 0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 q , gate charge (nc) -v , gate-source voltage (v) g gs v = -5v ds -10v -15v i = -0.14a d 1 2 3 5 10 20 40 0.005 0.03 0.1 0.3 1 - v , drain-source voltage (v) -i , drain current (a) rds(on) limit d dc ds 1s 100ms 10ms v = -4.5v single pulse r = see note 1b t = 25c q ja gs a 10s 0.1 0.2 0.5 1 2 5 10 20 0.5 1 3 5 10 20 40 -v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0 v gs c oss c rss 0.0001 0.001 0.01 0.1 1 10 200 0 10 20 30 40 50 single pulse time (sec) power (w) single pulse r =415c/w t = 25c q ja a
fdg 6320 c .rev d 0.0001 0.001 0.01 0.1 1 10 100 200 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 t - t = p * r (t) a j p(pk) t 1 t 2 q ja r (t) = r(t) * r r =415 c/w q ja q ja q ja figure 2 1 . transient thermal response curve . thermal characterization performed using the conditions described in note 1 . transient thermal response will change depending on the circuit board design. typical thermal characteristics: n & p-channel (continued)
trademarks acex? coolfet? crossvolt? e 2 cmos tm fact? fact quiet series? fast ? fastr? gto? hisec? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. tinylogic? uhc? vcx? isoplanar? microwire? pop? powertrench? qfet? qs? quiet series? supersot?-3 supersot?-6 supersot?-8
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